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18-bit, 100 ksps/500 ksps pulsar adcs in msop/lfcsp data sheet ad7989-1 / ad7989-5 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2014 analog devices, inc. all rights reserved. technical support www.analog.com features low power dissipation ad7989-1 400 w at 100 ksps (vdd only) 700 w at 100 ksps (total) ad7989-5 2 mw at 500 ksps (vdd only) 3.5 mw at 500 ksps (total) 18-bit resolution with no missing codes throughput: 100 ksps ( ad7989-1 )/500 ksps ( ad7989-5 ) inl: 1 lsb typical, 2 lsb maximum snr: 98 db at 1 khz, v ref = 5 v sinad: 97 db at 1 khz thd: ?120 db at 10 khz dynamic range: 99 db, v ref = 5 v true differential analog input range: v ref 0 v to v ref with v ref between 2.4 v and 5.1 v allows use of any input range easy to drive with the ada4941-1 no pipeline delay single-supply 2.5 v operation wi th 1.8 v/2.5 v/3 v/5 v logic interface spi-/qspi?-/microwire?-/dsp-compatible serial interface ability to daisy-chain multiple adcs 10-lead package: msop and 3 mm 3 mm lfcsp applications battery-powered equipment data acquisition systems medical instruments seismic data acquisition systems general description the ad7989-1 / ad7989-5 are 18-bit, successive approximation, analog-to-digital converters (adcs) that operate from a single power supply, vdd. they contain a low power, high speed, 18-bit sampling adc and a versatile serial interface port. on the cnv rising edge, the ad7989-1 / ad7989-5 sample the voltage difference between the in+ and in? pins. the voltages on these pins usually swing in opposite phases between 0 v and v ref . the reference voltage, ref, is applied externally and can be set independent of the supply voltage, vdd. its power scales linearly with throughput. the ad7989-1 / ad7989-5 are serial peripheral interface (spi) compatible, which features the ability, using the sdi input, to daisy-chain several adcs on a single 3-wire bus. it is compatible with 1.8 v, 2.5 v, 3 v, and 5 v logic, using the separate vio supply. the ad7989-1 / ad7989-5 are available in a 10-lead msop or a 10-lead lfcsp with operation specified from ?40c to +85c. table 1. msop, lfcsp 14-/16-/18-bit pulsar? adcs bits 100 ksps 250 ksps 400 ksps to 500 ksps 1000 ksps adc driver 18 1 ad7989-1 2 ad7691 2 ad7690 2 ad7982 2 ada4941-1 ad7989-5 2 ad7984 2 ada4841-1 16 1 ad7684 ad7687 2 ad7688 2 ada4941-1 ad7693 2 ada4841-1 16 3 ad7680 ad7685 2 ad7686 2 ad7980 2 ada4841-1 ad7683 ad7694 ad7988-5 2 ad7983 2 ada4841-1 ad7988-1 2 ada4841-1 14 3 ad7940 ad7942 2 ad7946 2 ada4841-1 1 true differential. 2 pin-for-pin compatible. 3 pseudo differential. typical applications circuit figure 1. ref gnd vdd in+ in? vio sdi/cs sck sdo cnv 1.8v to 5.5v ada4941-1 3- or 4-wire interface (spi, cs, daisy chain) 2.5v to 5v 2.5v 10v, 5v, .. ad7989-1/ ad7989-5 10232-001
ad7989- 1/ad7989 - 5 data sheet rev. 0 | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 typical applications circuit ............................................................ 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications .................................................................. 5 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configurations and function descriptions ........................... 8 typical p erformance characteristics ............................................. 9 terminology .................................................................................... 12 theory of operation ...................................................................... 13 circuit information .................................................................... 13 converter operation .................................................................. 13 typic al connection diagram .................................................... 14 analog inputs .............................................................................. 15 driver amplifier choice ........................................................... 15 single - to - differential driver .................................................... 16 voltage reference input ............................................................ 16 power supply ............................................................................... 16 digital interface .......................................................................... 16 cs mode, 3 - wire ........................................................................ 17 cs mode, 4 - wire ........................................................................ 18 chain mode ................................................................................ 19 applications information .............................................................. 20 interfacing to blackfin? dsp ..................................................... 20 layout .......................................................................................... 20 evaluating ad7989 - 1/ad7989 - 5 performance ..................... 21 outline dimensions ....................................................................... 22 ordering guide .......................................................................... 23 revision history 1/1 4 rev ision 0: initial versi on
data sheet ad7989- 1/ad7989 - 5 rev. 0 | page 3 of 24 specifications vdd = 2.5 v, vio = 2.3 v to 5.5 v, v ref = 5 v, t a = ? 40 c to +85c, unless otherwise noted. table 2 . parameter test conditions /comments min typ max unit resolution 18 bits analog input voltage range in+ ? in? ?v ref +v ref v absolute input voltage in+, in? ?0.1 v ref + 0.1 v common - mode input range in+, in? v ref 0.475 v ref 0.5 v ref 0.525 v analog input cmrr f in = 450 k hz 67 db leakage current at 25c acquisition phase 200 na input impedance see the analog input s section accuracy no missing codes 18 bits differential nonl inearity error ? 0.85 0.5 +1.5 lsb integral nonl inearity error ?2 1 +2 lsb transition noise v ref = 5 v 1.05 lsb 1 gain error, t min to t max 2 ? 0.023 + 0.004 + 0.023 % of fs gain error temperature drift 1 ppm/c zero error, t min to t max 2 100 + 700 v zero temperature drift 0.5 ppm/c power supply rejection ratio vdd = 2.5 v 5% 90 d b throughput ad7989 - 1 conversion rate 0 100 ksps ad7989 -5 conversion rate 0 500 k sps transient response full - scale step 400 ns ac accuracy dynamic range v ref = 5 v 97 99 db 3 v ref = 2.5 v 93 db 3 over sampled dynamic range 4 f o = 1 ksps 126 db 3 signal - to - noise ratio f in = 1 khz, v ref = 5 v, t a = 25c 95.5 98 db 3 f in = 1 khz, v ref = 2.5 v, t a = 25c 92.5 db 3 spurious - free dynamic range f in = 1 0 khz ?1 15 db 3 total harmonic distortion 5 f in = 1 0 khz ?1 20 db 3 signal - to - noise - and - distortion ratio f in = 1 khz, v ref = 5 v , t a = 25c 9 7 db 3 1 lsb means least significant bit. with the 5 v input range, 1 lsb is 38.15 v. 2 see the terminology section. these specifications include full temperature range variation but not the error contribution from the external reference. 3 all specifications expressed in decibels are referred to a full - scale input fsr and tested with an input signal at 0.5 db below full scale, unless otherwise specified. 4 dynamic range is obtained by oversampling the adc running at a throughput, f s , of 500 ksps followed by postdigital filtering with an output word rate of f o . 5 tested fully in production at f in = 1 khz.
ad7989- 1/ad7989 - 5 data sheet rev. 0 | page 4 of 24 vdd = 2.5 v, vio = 2.3 v to 5.5 v, ref = 5 v, t a = ? 40c to +85c, unless otherwise noted. table 3 . parameter test conditions /comments min typ max unit reference voltage range 2.4 5.1 v load current v ref = 5 v 250 a sampling dynamics ?3 db input bandwidth 10 mhz aperture delay vdd = 2.5 v 2 ns digital inputs logic levels v il vio > 3 v C 0.3 + 0.3 vio v vio 3 v C 0.3 +0.1 vio v v ih vio > 3 v 0.7 vio vio + 0.3 v vio 3 v 0.9 vio vio + 0.3 v i il ?1 +1 a i ih ?1 +1 a digital outputs data format serial , 18 bits , twos complement pipeline delay conversion results available immediately after completed conversion v ol i sink = +500 a 0.4 v v oh i source = ?500 a vio ? 0.3 v power supplies vdd 2.37 5 2.5 2.6 25 v vio specified performance 2.3 5.5 v vio range functional range 1.8 5.5 v standby current 1 , 2 vdd and vio = 2.5 v, 25c 0.35 a ad7989 - 1 power dissipation vdd = 2.625 v, v ref = 5 v, vio = 3 v total 10 ksps throughput 70 86 w 100 ksps throughput 700 860 w vdd only 400 w ref only 170 w vio only 130 w ad7989 -5 power dissipation vdd = 2.625 v, v ref = 5 v, vio = 3 v total 500 ksps throughput 3.5 4.3 mw vdd only 2 mw ref only 0.85 mw vio only 0.65 mw energy per conversion 7.0 nj/sample temperature range specified performance t min to t max ?40 +85 c 1 with all digital inputs forced to vio or ground as required. 2 during acquisition phase.
data sheet ad7989- 1/ad7989 - 5 rev. 0 | page 5 of 24 t iming s pecifications t a = ?40c to +85c, vdd = 2.37 v to 2.63 v, vio = 2.3 v to 5.5 v, unless otherwise not ed. see figure 2 and figure 3 for load conditions. table 4 . parameter symbol min typ max unit ad7989 -1 throughput rate 100 k sps conversion time: cnv rising edge to data available t conv 9500 n s acquisition time t acq 5 00 n s time between conversions t cyc 10 s ad7989 -5 throughput rate 500 k sps conversion time: cnv rising edge to data available t conv 1 6 00 ns acquisition time t acq 4 00 ns time between conversions t cyc 2 s cnv pulse width ( cs mode) t cnvh 500 ns sck period ( cs mode) t sck vio above 4.5 v 10.5 ns vio above 3 v 12 ns vio above 2.7 v 13 ns vio above 2.3 v 15 ns sck period (chain mode) t sck vio above 4.5 v 11.5 ns vio above 3 v 13 ns vio above 2.7 v 14 ns vio above 2.3 v 16 ns sck low time t sckl 4.5 ns sck high time t sckh 4.5 ns sck falling edge to data remains valid t hsdo 3 ns sck falling edge to data valid delay t dsdo vio above 4.5 v 9.5 ns vio above 3 v 11 ns vio above 2.7 v 12 ns vio above 2.3 v 14 ns cnv or sdi low to sdo d15 msb valid ( cs mode) t en vio above 3 v 10 ns vio above 2.3v 15 ns cnv or sdi high or last sck falling edge to sdo high impedance ( cs mode) t dis 20 ns sdi valid setup time from cnv rising edge ( cs mode) t ssdicnv 5 ns sdi valid hold time from cnv rising edge ( cs mode) t hsdicnv 2 ns sck valid setup time from cnv rising edge (chain mode) t ssckcnv 5 ns sck valid hold time from cnv rising edge (chain mode) t hsckcnv 5 ns sdi valid setup time from sck falling edge (chain mode) t ssdisck 2 ns sdi valid hold time from sck falling edge (chain mode) t hsdisck 3 ns
ad7989- 1/ad7989 - 5 data sheet rev. 0 | page 6 of 24 figure 2 . load circuit for digital interface timing figure 3 . voltage levels for timing 500 a i o l 500 a i oh 1.4v t o sdo c l 20pf 10232-002 x% vio 1 y% vio 1 v ih 2 v il 2 v il 2 v ih 2 t delay t delay 1 for vio 3.0v, x = 90 and y = 10; for vio > 3.0v, x = 70 and y = 30. 2 minimum v ih and maximum v il used. see digital inputs specifications in table 3. 10232-003
data sheet ad7989- 1/ad7989 - 5 rev. 0 | page 7 of 24 absolute maximum rat ings table 5 . parameter rating analog inputs in+, in? to gnd 1 ?0.3 v to v ref + 0.3 v or 130 ma supply voltage ref, vio to gnd ?0.3 v to +6.0 v vdd to gnd ?0.3 v to +3.0 v vdd to vio +3 v to ?6 v digital inputs to gnd ?0.3 v to vio + 0.3 v digital output to gnd ?0.3 v to vio + 0.3 v storage temperature range ?65c to +150c junction temperature 150c ja thermal impedance 10 - lead msop 200c/w 10 - lead lfcsp_wd 48.7c/w jc thermal impedance 10 - lead msop 44c/w 10 - lead lfcsp_wd 2.96c/w reflow soldering jedec standard (j - std - 020) 1 see the analog inputs section for an explanation of in+ and in?. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond th e maximum operating conditions for extended periods may affect product reliability. esd caution
ad7989- 1/ad7989 - 5 data sheet rev. 0 | page 8 of 24 pin configuration s and function descrip tions figure 4. 10 - lead msop pin configuration figure 5 . 10 - lead lfcsp pin configuration table 6 . pin function descriptions pin n o. mnemonic type 1 description 1 ref ai reference input voltage. the ref range is 2. 4 v to 5. 1 v. this pin is referred to the gnd pin and should be decoupled closely to the gnd pin with a 10 f capacitor. 2 vdd p power supply. 3 in+ ai differential positive analog input. 4 in? ai differential negative analog input. 5 gnd p power supply ground. 6 cnv di conversion input. this input has multiple functions. on its leading edge, it initiates the conversions and selects the interface mode of the device : chain mode or chip select ( cs ) mode. in cs mode, the sdo pin is enable d when cnv is low. in chain mode, the data is read when cnv is high. 7 sdo do serial data output. the conversion result is output on this pin. it is synchronized to sck. 8 sck di serial data clock input. when the device is selected, the conversion result is shifted out by this clock. 9 sdi/ cs di serial data input/chip select. this input has multiple functions . it selects the interface mode of the adc as follows: chain mode is selected if this pin is low during the cnv rising edge. in this mode, sdi/ cs is used as a data input to daisy - chain the conversion results of two or more adcs onto a single sdo line. the digital data level on sdi/ cs is output on sdo with a delay of 16 sck cycles. cs mode is selected if sdi/ cs is high during the cnv rising edge. in this mode, either sdi/ cs or cnv can enable the serial output signals when low. 10 vio p input/output interface digital power. this pin is n ominally at the same su pply as the host interface (1.8 v , 2.5 v, 3 v, or 5 v). ep exposed pad. for the lead frame chip scale package (lfcsp), the exposed pad can be connected to gnd. this connection is not required to meet the electrical performances. 1 ai = analog input, di = digital input, do = digital output, and p = power. ref 1 vdd 2 in+ 3 in? 4 gnd 5 vio 10 sdi/cs 9 sck 8 sdo 7 cnv 6 ad7989-1/ ad7989-5 t o p view (not to scale) 10232-004 notes: 1. the exposed p ad can be connected t o gnd. 1 ref 2 vdd 3 in+ 4 in? 5 gnd 10 vio 9 sdi_cs 8 sck 7 sdo 6 cnv ad7989-1/ ad7989-5 t o p view (not to scale) 10232-005
data sheet ad7989- 1/ad7989 - 5 rev. 0 | page 9 of 24 typical performance characteristics v dd = 2.5 v, v ref = 5.0 v, v io = 3.3 v . figure 6 . integral nonlinearity vs. code figure 7 . histogram of a dc input at the code center figure 8. ad7989 - 5 fft plot figure 9. differential nonlinearity vs. code figure 10 . histogram of a dc input at the code transition figure 11 . ad7989 - 1 fft plot 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 in l (lsb) 0 65536 131072 196608 262144 code positive inl: +0.79 lsb neg a tive inl: ?0.68 lsb 10232-006 60k 50k 40k 30k 20k 10k 0 counts 3fff0 3fff2 3fff4 3fff6 3fff8 3fffa 3fffc code in hex 0 0 29 745 881 43 0 0 7795 29064 50975 32476 9064 10232-007 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 0 50 100 150 200 250 frequency (khz) amplitude (db of full scale) 10232-008 f s = 500ksps f in = 1khz snr = 97.4361db sinad = 97.3577db thd = ? 1 14.42db 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 0 65536 131072 196608 262144 code dnl (lsb) positive inl: +0.46 lsb negative inl: ?0.49 lsb 10232-009 50k 45k 40k 35k 30k 25k 0 counts 0 1 2 3 4 5 6 7 8 9 a d code in hex 0 0 7 145 7 0 0 20k 15k 10k 5k 222 c b 16682 44806 43239 20013 3158 2793 10232-010 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 0 10 20 30 40 50 frequency (khz) amplitude (db of full scale) 10232-111 f s = 100ksps f in = 1khz snr = 97.2634db sinad = 97.145db thd = ?112.7db
ad7989-1/ad7989-5 data sheet rev. 0 | page 10 of 24 figure 12. snr vs. input level figure 13. snr, sinad, and enob vs. reference voltage figure 14. snr vs. temperature figure 15. sinad vs. frequency figure 16. thd, sfdr vs. reference voltage figure 17. thd vs. temperature 100 99 98 97 96 95 94 93 92 91 90 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 input level (db) snr (db referred to full scale) 10232-011 100 95 90 85 80 snr, sinad (db) 2.25 2.75 3.25 3.75 4.25 4.75 5.25 reference voltage (v) 18 17 16 15 14 enob (bits) enob snr, sinad 10232-012 100 98 96 94 92 90 snr (db) ?55 ?35 ?15 5 25 45 65 85 105 125 temperature (c) 10232-013 100 95 90 85 80 0.1 1 10 100 1k frequency (khz) sinad (db) 10232-014 ? 100 ?105 ?110 ?115 ?120 ?125 ?130 thd (db) 2.25 2.75 3.25 3.75 4.25 4.75 5.25 reference voltage (v) 130 125 120 115 110 105 100 sfdr (db) thd sfdr 10232-015 ? 115 ?117 ?119 ?121 ?123 ?125 thd (db) ?55 ?35 ?15 5 25 45 65 85 105 125 temperature (c) 10232-016
data sheet ad7989- 1/ad7989 - 5 rev. 0 | page 11 of 24 figure 18 . operating currents vs. vdd voltage ( ad7989 - 5) figure 19 . thd vs. frequency figure 20 . operating currents vs. temperature ( ad7989 - 5) figure 21 . operating currents vs. vdd voltage ( ad7989 - 1) figure 22 . power - down currents vs. temperature figure 23 . operating currents vs. temperature ( ad7989 - 1 ) 0 . 7 0 . 6 0 . 5 0 . 4 0 . 3 0 . 2 0 . 1 0 v d d vo lt a g e ( v) i vdd i ref i vio oper a ting currents (ma) 2.375 2.425 2.475 2.525 2.575 2.625 10232- 1 18 ?80 ?85 ?90 ?95 ?100 ?105 ?110 ?115 ?120 ?125 0.1 1 10 100 1k frequency (khz) thd (db) 10232-017 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 oper a ting currents (ma) i vdd i ref i vio t e m p e r a t ur e ( c ) ?55 ?35 ?15 5 25 45 65 85 105 125 10232-120 0 .1 4 0 .1 2 0 .1 0 0 .0 8 0 .0 6 0 .0 4 0 .0 2 0 vd d volt a g e ( v) i vdd i ref i vio oper a ting currents (ma) 2.375 2.425 2.475 2.525 2.575 2.625 10232-121 8 7 6 5 4 3 2 1 0 power-down currents (a) ?55 ?35 ?15 5 25 temperature (c) 45 65 85 105 125 i vdd + i vio 10232-018 0 .1 4 0 .1 2 0 .1 0 0 0 8 0 .0 6 0 .0 4 0 . 0 2 0 oper a ting currents (ma) i vdd i ref i vio t e m p e r a t ur e ( c ) ?55 ?35 ?15 5 25 45 65 85 105 125 10233-123
ad7989- 1/ad7989 - 5 data sheet rev. 0 | page 12 of 24 terminology integral nonlinearity error (inl) inl refers to the deviation of each individua l code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. the deviat ion is measured from the middle of each code to the true straight line (see figure 25). differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. dnl is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. zero error zero error is the difference between the ideal midscale voltage, that is, 0 v, and the actual voltage producing the midscale output code, that is, 0 lsb. gain error the first transition (from 100 00 to 100 01) should occur at a level ? lsb above nominal negative full scale (?4.999981 v for the 5 v range). the last transition ( from 011 10 to 011 11) occurs for an analog voltage 1? lsb below the nominal full scale (+4.999943 v for the 5 v range). the gain error is the deviation of the difference between the actual level of the last transition and the actual level of the firs t transition from the difference between the ideal levels. spurious - free dynamic range (sfdr) sfdr is the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to sinad as follows enob = ( sinad db ? 1.76)/6.02 and is expressed in bits. noise - free code resolution noise - free code resolution is the number of bits beyond which it is impossible to dist inctly resolve individual codes. it is calculated as noise - free code resolution = log 2 (2 n / peak - to - peak noise ) and is expressed in bits. effective resolution effective resolution is calculated as effective resolution = log 2 (2 n / rms input noise ) and is expressed in bits. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full - scale input signal and is expressed in decibels. dynamic range dynamic range is the ratio of the rms value o f the full scale to the total rms noise measured with the inputs shorted together. the value for dynamic range is expressed in decibels. it is measured with a signal at ?60 db so that it includes all noise sources and dnl artifacts. signal -to - noise ratio ( snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signal -to - noise - and - distortion (sinad) ra tio sinad is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components that are less than the nyquist frequency, including harmonics but excluding dc. the value of sinad is expressed in decibels. aperture delay aperture delay is the measure of the acquisition performance and is the time between the rising edge of the cnv input and when the input signal is held for a conversion. transient response transient response is the time required for the adc to accurately a cquire its input after a full - scale step function is applied.
data sheet ad7989- 1/ad7989 - 5 rev. 0 | page 13 of 24 th e ory of operation figure 24 . adc simplified schematic circuit information the ad7989 - 1 / ad7989 - 5 are high speed , low power, single - supply, precise , 18- bit adc s using a successive approximation architecture. the ad7989 - 5 is capable of converting 500,000 samples per second (500 ksps) , whereas the ad7989 - 1 is capable of converting 1 00, 000 samples per second (1 00 k sps) , and they power down between conversions. when operating at 10 0 ksps, the adc typically consumes 7 0 0 w, making the ad7989 - 1 ideal for battery - powered applications. the ad7989 - 1 / ad7989 - 5 provide the user with an on - chip track - and - hold amplifier and do not exhibit any pipeline delay or latency, making these devices ideal for multiple multiplexed channel applications. the ad7989 - 1 / ad7989 - 5 can be interfaced to any 1.8 v to 5 v digital logic family. it is available in a 10 - lead msop or a tiny 10- lead lfcsp that allows space savings and flexible configurations. converter operation the ad7989 - 1 / ad7989 - 5 are a successive appr oximation adc s based on a charge redistribution digital - to - analog converter ( dac ) . figure 24 shows the simplified schematic of the adc. the capacitive dac consists of two identical arrays of 18 binary - weighted capacitors, which are connected to the two comparator inputs. during the acquisition phase, terminals of the array tied to the input of the comparator are connected to gnd via sw+ and sw?. all independent switches are connected to the analog inputs. th erefore , the capacitor arrays are used as sampling capacitors and acquire the analog signal on the in+ and in? inputs. when the acquisition phase is complete and the cnv input goes high, a conversion phase is initiated. when the conversion phase begins, sw+ and sw? are opened first. the two capacitor arrays are then disconnected from the inputs and connected to the gnd input. therefore, the differential voltage between the in+ and i n? inputs captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. by switching each element of the capacitor array between gnd and ref, the comparator input varies by binary - weighted vo ltage steps (v ref /2, v ref /4 ... v ref /262 , 144). the control logic toggles these switches, starting with the msb, to bring the comparator back into a balanced condition. after the completion of this process, the device returns to the acquisition phase , and the control logic generates the adc output code. because the ad7989 - 1 / ad7989 - 5 ha ve an on - board conversion clock, the serial clock, sck, is not required for the conversion process. c o m p c o n t r o l l o g i c s w i t c h es c o n t r o l b u s y o u t p u t c o d e c n v c c 2c 65,536c 4c 131,072c lsb sw+ msb lsb sw? msb c c 2c 65,536c 4c 131,072c in+ ref gnd in? 10232-020
ad7989- 1/ad7989 - 5 data sheet rev. 0 | page 14 of 24 transfer functions the ideal transfer characteris tic for the ad7989 - 1 / ad7989 - 5 is shown in figure 25 and table 7 . figure 25 . adc ideal transfer function table 7 . output codes and ideal input voltages description analog input v ref 5 v digital outp ut code ( he ) + fsr C 1 lsb +4.999962 v 0x 1ffff 1 midscale + 1 lsb +38.15 v 0x 00001 midscale 0 v 0x 00000 midscale C 1 lsb ?38.15 v 0x 3ffff C fsr + 1 lsb ?4.999962 v 0x 20001 C fsr ?5 v 0x 20000 2 1 this is also the code for an overranged analog input (v in+ ? v in? above v ref ? v gnd ). 2 this is also the code for an underranged analog input (v in+ ? v in? below v gnd ). typical connection d iagram figure 26 shows an example of the recommended connection diagram for the ad7989 - 1 / ad7989 - 5 when multiple supplies are available. figure 26 . typical applicat ion diagram with multiple supplies 100...000 100...001 100...010 01 1...101 01 1... 1 10 01 1... 11 1 adc code (twos complement) analog input +fsr ? 1.5 lsb +fsr ? 1 lsb ?fsr + 1 lsb ?fsr ?fsr + 0.5 lsb 10232-021 2.7nf 20? v? 0v to v ref v+ 4 2.7nf 20? v? v ref to 0v v+ 4 10f 2 ref 1 ref vdd vio gnd in+ in? sck sdo cnv ad7989-1/ ad7989-5 100nf 100nf 3-wire interface 2.5v 1.8v to 5.5v v+ ada4841-x 2, 3 1 see the voltage reference input section for reference selection. 2 c ref is usually a 10f ceramic capacitor (x5r). see the recommended layout in figure 39 and figure 40. 3 see the driver amplifier choice section. 4 optional filter. see the analog inputs section. sdi/cs 10232-022
data sheet ad7989- 1/ad7989 - 5 rev. 0 | page 15 of 24 analog input s figure 27 shows an equivalent circuit of the input structure of the ad7989 - 1 / ad7989 - 5 . the two diodes, d1 and d2, provide esd protection for the analog inputs , in+ and in?. care must be taken to ensure that the analog input signal does not exceed the reference input voltage (ref) by more than 0.3 v . if the analog input signal exceeds this le vel, the diodes be come forward - bias ed and start conducting current. these diodes can handle a forward - biased current of 130 ma maximum. however, if the supplies of the input buffer (for example, the supplies of the ada4841 - x in figure 26) are different from those of ref , the analog input signal may eventually exceed the supply rails by more than 0.3 v. in such a case (for example, an input buffer with a short circuit ) , the current limitation can be used to protect the device . figure 27 . equivalent analog input circuit the analog input structure allows the sampling of the true differential signal between in+ and in?. by using these differential inputs, signals common to both inputs are rejected. figure 28 . analog input cmrr vs. frequency during the acquisition phase, the impedance of the analog inputs (in+ or in?) can be modeled as a parallel combination of c apacitor c pin and the network formed by the series connection of r in and c in . c pin is primarily the pin capacitance. r in is typically 400 ? and is a lumped component composed of serial resistors and the on resistance of the switches. c in is typically 30 pf and is mainly the adc sampling capacitor. during the sampling phase, when the switches are close d, the input impedance is limited to c pin . r in and c in make a one - pole, low - pass filter that reduces undesirable aliasing effects and limits noise. when the source impedance of the driving circuit is low, the ad79 89- 1 / ad7989 - 5 can be driven directly. large source impedances significantly affect the ac performance, especially thd. the dc performances are less sensitive to the input impedance. the maximum source impedance depends on the amount of thd that can be tolerated. the thd degrades as a function of the source impedance and the maximum input frequency. driver amplifier cho ice although the ad7989 - 1 / ad7989 - 5 is easy to drive, the driver amplifier must meet the following requirements: ? the noise generated by the driver amplifier must be kept as low as possible to preserve the snr and transition noise performance of the ad7989 - 1 / ad7989 - 5 . the noise from the driver is filtered by the one - p ole, low - pass filter of the ad7989 - 1 / ad7989 - 5 analog input circuit made by r in and c in or by the external filter, if one is used. because the typical noise of the ad7989 - 1 / ad7989 - 5 is 40 v rms, the snr degradation due to the amplifier is ? ? ? ? ? ? ? ? ? ? ? ? + = ? 2 2 ) ( 2 40 40 log 20 n 3db loss ne f snr ? where: f C 3db i s the input bandwidth , in megahertz, of the ad7989 - 1 / ad7989 - 5 (10 mhz) or the cutoff frequency of the input filter, if one is used. n is the noise gain of the amplifier (for examp le, 1 in buffer configuration). e n is the equivalent input noise voltage of the op amp, in nv/hz. ? for ac ap plications, use a driver with a thd performance commensurate with the ad7989 - 1 / ad7989 - 5 . ? for multichannel multiplexed applications, the driver amplifier and the ad7989 - 1 / ad7989 - 5 analog input circuit must settle for a full - scale step onto the capacitor array at a n 18 - bit level (0.0004% , 4 ppm). in the data sheet of the amplifier , settling at 0.1% to 0.01% is more commonly specified. this settling may differ significantly from the settling time at a n 18 - bit level and must be verified prior to driver selection. table 8 . recommended driver amplifiers amplifier typical application ada4941 -1 very low noise, low power , single to differential ada4841 -1 / ada4841 -2 very low noise, small, and low power ad8021 very low noise and high frequency ad8022 low noise and high frequency op184 low power, low noise , and low frequency ad8655 5 v single supply, low noise ad8605 , ad8615 5 v single supply, low power c pin ref r in c in d1 d2 in+ or in? gnd 10232-023 90 85 80 75 70 65 60 1 10 100 1k 10k frequency (khz) cmrr (db) 10232-024
ad7989- 1/ad7989 - 5 data sheet rev. 0 | page 16 of 24 single - to - differential driver for applications using a single - ended analog signal, either bipolar or unipolar, the ada4941 - 1 single - ended - to - differential driver allows a differential input to the device . the schematic is shown in figure 29. r1 and r2 set the attenuation ratio between the input range and the adc range (v ref ). r1, r2 , and c f are chosen depending on the desired input res istance, signal bandwidth, anti aliasing , and noise contribution. for example, for the 10 v range with a 4 k? impedance, r2 = 1 k? and r1 = 4 k? . r3 and r4 set the common mode on the in ? input, and r5 and r6 set the common mode on the in+ input of the adc . make sure that th e common mode is close to v ref /2. for example, for the 10 v range with a single supply, r3 = 8.45 k?, r4 = 11.8 k? , r5 = 10.5 k?, and r6 = 9.76 k? . figure 29 . single - ended - to- differential driver circuit voltage reference in put the ad7989 - 1 / ad7989 - 5 voltage refe rence input, ref, has a dynamic input impedance and must, therefore , be driven by a low impedance source with efficient decoupling between the ref and gnd pins, as explained in the layout section. when ref is driven by a very low impedance source ( for example, a reference buffer using the ad8031 or the ad8605 ) , a 10 f (x5 r, 0805 size) ceramic chip capacitor is appropriate for optimum performance. if an unbuffered reference voltage is used, the decoupling value depends on the reference used. for instance, a 22 f (x5r, 1206 size) ceramic chip capacitor is appropriate for op timum performance using a low temperature drift adr43x reference. if desired, a reference decoupling capacitor with values as small as 2.2 f can be used with a minimal impact on performa nce, especially dnl. regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nf) between the ref and gnd pins. power supply the ad7989 - 1 / ad7989 - 5 use two power supply pins: a core supply ( vdd ) and a digital input/output interface supply ( vio ) . vio allows direct interface with any logic between 1.8 v and 5.5 v . to reduce the number of supplies needed, vio and vdd can be tied together. the ad7989 - 1 / ad7989 - 5 are independent of power supply sequencing between vio and vdd. additionally, they are insensitive to power supply variations over a wide frequency range , as shown in figure 30. figure 30 . ps rr vs. frequency the ad7989 - 1 / ad7989 - 5 power down automatically at the end of each conversion phase . digital interface alt hough the ad7989 - 1 / ad7989 - 5 ha ve a reduced number of pins, they offer flexibility in their serial interface modes. when in cs mode, the ad7989 - 1 / ad7989 - 5 are compatible with spi, qspi, digital hosts , and dsps . in t his mode, the ad7989 - 1 / ad7989 - 5 can use either a 3 - wire or 4 - wire interface . a 3 - wire interface using the cnv, sck, and sd o signa ls minimizes wiring connections, which is useful, for instance, in isolated applications. a 4 - wire interface using the sdi/ cs , cnv, sck, and sdo signals allows cnv, which initiates the conversions, to be independent of the readback timing (sdi). this is useful in low jitter sampling or simultaneous sampling applications. when in chain mode, the ad7989 - 1 / ad7989 - 5 provide a daisy - chain feature using the sdi input for cascading multiple adcs on a single data line , similar to a shift register. the mode in which the device operates depends on the sdi/ cs level when the cnv rising edge occurs. cs mode is selected if sdi/ cs is high , and chain mode is selected if sdi/ cs is low. the sdi/ cs hold time is such that when sdi/ cs and cnv are connected together, chain mode is always selected. the user must time out the maximum conversion time prior to readback. 20? 20? 10f r1 100nf +2.5v +5v ref +5.2v ?0.2v c f r2 r4 r6 10v, 5v, .. r3 r5 ref vdd gnd in+ in? ad7989-1/ ad7989-5 2.7nf 2.7nf ada4941 in fb outp outn ref 100nf 10232-025 95 90 85 80 75 70 65 60 psrr (db) 1 10 100 1k frequency (khz) 10232-026
data sheet ad7989- 1/ad7989 - 5 rev. 0 | page 1 7 of 24 cs mode , 3 - wire this mode is usually used when a single ad7989 - 1 / ad7989 - 5 is connected to an spi - compatible digital host. the connection diagram is shown in figure 31, and the correspon ding timing is given in figure 32. with sdi/ cs tied to vio, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. when the conversion is complete, the ad7989 - 1 / ad7989 - 5 enter the acquisition phase and power down. when cnv goes low, the msb is output onto sdo. the remaining data bits are clocked by s ubsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allow s a faster reading rate , provided that it has an acceptable hold time. after the 18 th sck falling edge or when cnv goes high ( whichever occurs first) , sdo returns to high impedance. figure 31 . cs mode , 3- wire connection diagram (sdi high) figure 32 . cs mode , 3 - wire serial interface timing (sdi high) ad7989-1/ ad7989-5 sdo cnv sck convert data in clk digital host vio sdi/cs 10232-027 sdo d17 d16 d15 d1 d0 t dis sck 1 2 3 16 17 18 t sck t sckl t sckh t hsdo t dsdo cnv conversion acquisition t conv t cyc acquisition t acq t en sdi/cs = 1 10232-028
ad7989- 1/ad7989 - 5 data sheet rev. 0 | page 18 of 24 cs mode , 4 - wire this mode is usually used when multiple ad7989 - 1 / ad7989 - 5 device s are connected to an spi - compatible dig ital host. a connection diagram example using two ad7989 - 1 / ad7989 - 5 device s is shown in figure 33, and the corresponding timing is given in figure 34. with sdi high, a rising edge on cnv initiates a conversion, selects sdi/ cs mode, and forces sdo to high impedance. in this mode, cnv must be held high during the conversion phase and the subsequent data readback . ( if sdi/ cs and cnv are low, sdo is dri ven low . ) prior to the minimum conversion time, sdi/ cs can be used to select other spi devices, such as analog multiplexers, but sdi/ cs must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time. when the conversion is complete, the ad7989 - 1 / ad7989 - 5 enter the acquisition phase and power down. each adc result can be read by bringing its sdi/ cs input low , which consequently outputs the msb onto sdo. the remai ning data bits are then clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allow s a faster reading rate , provided that it has an acceptable hold time. after the 18 th sck falling edge or when sdi/ cs goes high ( whichever occurs first) , sdo returns to high impedance and another ad7989 - 1 / ad7989 - 5 can be read. figure 33 . cs mode , 4- wire connection diagram figure 34 . cs mode , 4- wire serial interface timing ad7989-1/ ad7989-5 sdo cnv sck convert data in clk digital host cs1 cs2 ad7989-1/ ad7989-5 sdo cnv sck sdi/cs sdi/cs 10232-029 sdo d17 d16 d15 d1 d0 t dis sck 1 2 3 34 35 36 t hsdo t dsdo t en conversion acquisition t conv t cyc t acq acquisition cnv t ssdicnv t hsdicnv d1 16 17 t sck t sckl t sckh d0 d17 d16 19 20 18 sdi/cs (cs1) sdi/cs (cs2) 10232-030
data sheet ad7989- 1/ad7989 - 5 rev. 0 | page 19 of 24 chain mode this mode can be used to daisy - chain multiple ad7989 - 1 / ad7989 - 5 device s on a 3 - wire serial interface. this feature is useful for reducing component count and wiring connections, for example , in isolated multiconverter applications or for systems with a limited interfacing capacity. data readback is analogous to clocking a sh ift register. a connection diagram example using two ad7989 - 1 / ad7989 - 5 device s is shown in figure 35, and the corresponding timing is given in figure 36. when sdi/ cs and cnv are low, sdo is driven low. with sck low, a rising edge on cnv initiates a convers ion, and selects the chain mode . in this mode, cnv is held high during the conversion phase and the subsequent data readback. when the conversion is complete, the msb is output onto sdo and the ad7989 - 1 / ad7989 - 5 enter the acquisition phase and power down. the remaining data bits stored in the internal shif t register are clocked by subsequent sck falling edges. for each adc, sdi feeds the input of the internal shift register and is clocked by the sck falling edge. each adc in the chain outputs its data msb first, and 18 n clocks are required to read back t he n adcs. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allow s a faster reading rate and , consequentl y, more ad7989 - 1 / ad7989 - 5 device s in the chain, provided that the digital host has an acceptable hold time. the maximum conversion rate may be reduced due to the total readback time. figure 35 . chain mode connection diagram figure 36 . chain mode serial interface timing convert data in clk digital host ad7989-1/ ad7989-5 sdo cnv b sck ad7989-1/ ad7989-5 sdo cnv a sck sdi/cs sdi/cs 10232-031 d a 17 d a 16 d a 15 sck 1 2 3 34 35 36 t ssdisck t hsdisck t en conversion acquisition t conv t cyc t acq acquisition cnv d a 1 16 17 t sck t sckl t sckh d a 0 19 20 18 sdo b d b 17 d b 16 d b 15 d a 1 d b 1 d b 0 d a 17 d a 16 t hsdo t dsdo t ssckcnv t hsckcnv d a 0 sdi/cs a = 0 sdo a = sd i /cs b 10232-032
ad7989- 1/ad7989 - 5 data sheet rev. 0 | page 20 of 24 application s information interfacing to black fin? dsp the ad7989 - 1 / ad7989 - 5 can easily connect to a dsp spi or sport. the spi configuration is straightforward using the standard spi interface , as shown in figure 37. figure 37 . typical connection to blackfin spi interface similarly, the sport interface can be used to interfac e to this adc. the sport interface has some benefits in that it can use direct memory access (dma) and provides a lower jitter cnv signal generated from a hardware counter. some glue logic may be required between sport and the ad7989 - 1 / ad7989 - 5 interface . the evaluation board fo r the ad7989 - 1 / ad798 9 - 5 interfaces directly to the sport of the blackfin - based ( adsp - bf527 ) sdp board. the configuration used for the sport interface requires the addition of some glue logic as shown in figure 3 8 . the sck input to the adc was gated off when cnv was high to keep the sck line static while converting the data, thereby ensuring the best in tegrity of the result. this approach uses an and gate and a not gate for the sck path. the other logic gates used on the rsclk and rfs paths are for delay matching purposes and may not be necessary when path lengths are short. this is one approach to usin g the sport interface for this adc ; there may be other solutions similar to this approach. figure 38 . evaluation board connection to blackfin sport interface layout design t he printed circuit board that houses the ad7989 - 1 / ad7989 - 5 so that the analog and digital sections are separated and confined to certain areas of the board. the pinout of the ad7989 - 1 / ad7989 - 5 , with its analog signals on the left side and its digital signals on the right side, eases this task. avoid running digital lines under the d evice because these couple noise onto the die, unless a ground plane under the ad7989 - 1 / ad7989 - 5 is used as a shield. do not run f ast switching signals, such as cnv or clocks, near analog signal paths. avoid c rossover of digital and analog signals . using a t least one ground p lane is recommended . it can be common or split between the digital and analog section s . in the latter case, join the planes underneath the ad7989 - 1 / ad7989 - 5 device s. the ad7989 - 1 / ad7989 - 5 voltage reference input , ref , has a dynamic input impedance . decouple ref with minimal parasitic inductances by placing the reference decoupling ceramic capacitor close to, but ideally right up against, the ref and gnd pins and connect ing them with wide, low impedance traces. finally, decouple the power supplies of the ad7989 - 1 / ad7989 - 5 , vdd and v io, with ceramic capacitors, typically 100 nf, placed close to the ad7989 - 1 / ad7989 - 5 and connected using short , wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines. an example of a layout following these rules is shown in figure 39 and figure 40. ad7989-1/ ad7989-5 sck sdo cnv spi_clk spi_miso spi_mosi 10232-035 d s p sck sdo cnv tsclk dr tfs rfs rsclk vdrive ad7989-1/ ad7989-5 10232-045 blackfin d s p
data sheet ad7989-1/ad7989-5 rev. 0 | page 21 of 24 evaluating ad7989-1 / ad7989-5 performance other recommended layouts for the ad7989-1 / ad7989-5 are outlined in ug-340 , the user guide of the evaluation board for the ad7989-1 / ad7989-5 ( EVAL-AD7989-5SDZ ). the evaluation board package includes a fully assembled and tested evaluation board, the user guide, and software for controlling the board from a pc via the eval-sdp-cb1z . figure 39. recommended layout of the ad7989-1 / ad7989-5 (top layer) figure 40. recommended layout of the ad7989-1 / ad7989-5 (bottom layer) ad7989-1/ ad7989-5 10232-033 10232-034
ad7989- 1/ad7989 - 5 data sheet rev. 0 | page 22 of 24 ou tline dimensions figure 41 . 10 - lead mini small outline package [msop] (rm - 10) dimensions shown in millimeters figure 42 . 10 - lead lead frame chip scale package [lfcsp_wd] 3 mm 3 mm body, very very thin, dual lead (cp - 10 - 9) dimensions shown in millimeters c o m p l i a n t t o j e d e c s t a n d a r d s m o - 1 8 7 - b a 0 9 1 7 0 9 - a 6 0 0 . 7 0 0 . 5 5 0 . 4 0 5 1 0 1 6 0 . 5 0 b s c 0 . 3 0 0 . 1 5 1 . 1 0 m a x 3 . 1 0 3 . 0 0 2 . 9 0 c o p l a n a r i t y 0 . 1 0 0 . 2 3 0 . 1 3 3 . 1 0 3 . 0 0 2 . 9 0 5 . 1 5 4 . 9 0 4 . 6 5 p i n 1 i d e n t i f i e r 1 5 m a x 0 . 9 5 0 . 8 5 0 . 7 5 0 . 1 5 0 . 0 5 2.48 2.38 2.23 0.50 0.40 0.30 10 1 6 5 0.30 0.25 0.20 pin 1 index are a sea ting plane 0.80 0.75 0.70 1.74 1.64 1.49 0.20 ref 0.05 max 0.02 nom 0.50 bsc exposed pa d 3.10 3.00 sq 2.90 pin 1 indic a t or (r 0.15) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. coplanarity 0.08 02-05-2013-c t op view bottom view 0.20 min
data sheet ad7989- 1/ad7989 - 5 rev. 0 | page 23 of 24 ordering guide model 1 , 2 , 3 temperature range package description package option ordering quantity branding ad7989 - 1brmz ?40c to +85c 10 - lead msop, tube rm -10 50 c76 ad7989 - 1brmz -rl7 ?40c to +85c 10 - lead msop, 7 tape and reel rm -10 1,000 c76 ad7989 - 1bcpz -rl7 ?40c to +85c 10 - lead lfcsp_wd, 7 tape and reel cp -10 -9 1,500 c80 ad7989 - 1bcpz -r2 ?40c to +85c 10 - lead lfcsp_wd cp -10 -9 250 c80 ad7989 - 5brmz ?40c to +85c 10 - lead msop, tube rm -10 50 c7n ad7989 - 5brmz -rl7 ?40c to +85c 10 - lead msop, 7 tape and reel rm -10 1,000 c7n ad7989 - 5bcpz -rl7 ?40c to +85c 10 - lead lfcsp_wd, 7 tape and reel cp -10 -9 1,500 c7y ad7989 - 5bcpz -r2 ?40c to +85c 10 - lead lfcsp_wd cp -10 -9 250 c7y eval - ad7989 - 5sdz evaluation board with ad7989 -5 populated; use for evaluation of both ad7989 - 1 and ad7989 -5 eval - sdp - cb1z system demonstration board, used as a controller board for data transfer via usb interface to pc 1 z = rohs compliant part. 2 the eval - ad7989 - 5sdz board can be used as a standalone evaluation board or in conjunction with the eval - sdp - cb1z for evaluation/demonstration purposes. 3 the eval - sdp - cb1z board allows a pc to control and communicate with all analog devices, inc., evaluation boards ending in the sd designator.
ad7989- 1/ad7989 - 5 data sheet rev. 0 | page 24 of 24 notes ? 2014 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10232 - 0 - 1/14(0)

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